1. Field of the Invention
The invention relates to a hardware component graph (HCG) to hardware description language (HDL) translation method and, more particularly, to a hardware component graph (HCG) to Very High Speed Integrated Circuit Hardware Description Language (VHDL) translation method.
2. Description of Related Art
Typically hardware description languages such as VHDL, Verilog cannot directly describe the programming logic and executing the flow of a high-level programming language. Accordingly, the high-level programming language is translated into an activity diagram (AD) defined in a unified modeling language (UML). The AD is a flow description diagram that represents the programming logic and executing flow of a high-level programming language. However, the AD is not associated with physical hardware components and cannot be translated directly into a hardware description language, unless the AD is first translated into a hardware component graph (HCG). Accordingly, components of such a HCG do not have corresponding VHDL components, and the HCG cannot be translated into accurate VHDL codes. Thus, the known method cannot translate a high-level programming language into a corresponding HDL.
Therefore, it is desirable to provide an improved method to mitigate and/or obviate the aforementioned problems.